1. Field of the Invention
The present invention relates to an electronic device test apparatus for testing semiconductor integrated circuit devices and various other electronic devices and a method of configuring an electronic device test apparatus, more particularly relates to an electronic device test apparatus enabling optimization so that the efficiency of the test apparatus as a whole does not fall due to the performance of a handler even when maximum number of simultaneous measurements has been changed due to the relationship between the maximum number of testable pins of the tester and the number of pins of an electronic device under test (DUT) and a method of configuring such an electronic device test apparatus.
2. Description of the Related Art
In the process of production of semiconductor devices, an electronic device test apparatus becomes necessary for testing the finally produced IC chip or other electronic device. This type of electronic device is tested by setting the test environment to an ordinary temperature, high temperature, or low temperature environment, inputting a test pattern to the IC chip and operating it in that temperature state, and examining the response pattern. This is because the characteristics of an IC chip have to be guaranteed to enable good operation both under ordinary temperature or a high temperature or low temperature.
A general electronic device test apparatus of the related art is comprised of a test head provided with a tester in which a program for transmitting a test pattern and examining the response pattern is stored and contact terminals for electrically connecting this tester and a DUT and a handler for successively conveying a large number of DUTs to the contact terminals of the test head and physically classifying the DUTs finished being tested in accordance with the test results. Further, it sets DUTs at the handler for conveyance to the test head where it presses the DUTs against the contact terminals of the test head for electrical contact for the purpose of the desired operating test.
One of the aspects of the performance of a tester is the maximum number of testable pins. This means the number of signal terminals enabling output from and input to that tester. The maximum number of devices able to be simultaneously tested is determined from the relationship of this maximum number of testable pins and the number of pins (number of terminals) of the DUT. For example, when the maximum number of testable pins of the tester is 100 and the number of terminals of the DUT is 20, the maximum number of simultaneous measurements is 100÷20=5.
On the other hand, one of the aspects of the performance of a handler is its throughput. This is the number of the DUTs which that handler can handle per unit time. That is, this shows the mechanical operation speed by which the handler sets the pre-tested DUTs, aligns them before the test head, conveys them to the test head, pushes them against the contact terminals, then arranges them classified in accordance with the test results. The larger the throughput, the higher the productivity of the handler. However, even with a handler with a large throughput, if the time for pressing the DUTs against the contact terminals for transfer of operating signals (hereinafter also referred to as the “test time”) is long, so-called “waiting time” will occur in the conveyance system, so the maximum throughput will not necessarily be realized. That is, depending on the test time, the maximum throughput will sometimes be realized and other times will not. On the other hand, there is the difficulty that the higher the speed of the conveyance system, the greater the cost of the equipment.
As explained above, in an electronic device test apparatus, if the numbers of terminals of the DUTs (numbers of pins) differ, the maximum number of simultaneous measurements will also change. Therefore, to obtain the desired productivity, testers with different maximum numbers of measurable pins would become necessary. If using common equipment for the testers, handlers of specifications with different throughputs become necessary. However, if not selecting the handler with the optimum throughput from the relationship with the test time, the result will not be efficient. Further, due to the target test temperature (low temperature, ordinary temperature, or high temperature) or testable temperature range, adiabatic structures or thermostats (chambers) with different components or temperature regulators become necessary.
Further, electronic device test apparatuses come in shapes or IC pin configurations differing depending on the types of the DUTs. Switching change kits enables conveyance by common test trays.
Further, at the tester side with the test heads, there are testers of a plurality of types of system configurations designed for diverse DUTs. Therefore, the maximum number of testable pins (number of channels of tester) provided at the test head differs tremendously such as for example 256, 512, 1024, and other channels.